Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond

Abstract

We demonstrated several new approaches to enable multiple threshold voltage (multi-Vt) solutions by volumeless multi-Vt integrations and metal multi-Vt integrations for 2nm high-performance nanosheet (NS) technology and beyond. Selective layer reduction 1 (SLR1) is proposed to control N/P boundary by solving the undercut of thin layer patterning on top of Tsus (space between stack NS) pinchoff (TPO) scheme. A new etch process is also developed to solve plasma damage for thin layer integration. Selective layer reduction 2 (SLR2) is used to control N/P boundary of thick work function metal (WFM) integration to offer low Vt device. With improved dual-dipoles integration, 4 pairs of Vts are enabled for 2 nm high-performance NS technology and beyond.