Hazar Yueksel, Ramon Bertran, et al.
MLSys 2020
Vertical-Transport Nanosheet Technology (VTFET) is an attractive solution to enable aggressive CMOS scaling in the sub-45nm contacted gate pitch (CGP) regime. By decoupling the classic tradeoff of S/D contacts, gate length & CGP, VTFET technology overcomes middle-of-the-line (MOL) dominated performance pinch-points by providing independent optimization of the contact dimension & device width as well as significant Ceff reduction [1]. VTFET offers an attractive solution at sub-45nm CGP, however it introduces unique design challenges that need to be optimized to take full power-performance-area (PPA) entitlement. In this paper, we present for the first time a logic standard cell architecture to enable a competitive VTFET technology. First, we introduce key features of the VTFET architecture which enable significant advantages relative to leading-edge competitive technologies. Further we describe key Design Technology Co-Optimization (DTCO) scaling knobs that naturally lend themselves to VTFET such as single fins, buried power rails and gate-contact super vias can achieve competitive area scaling vs. an industry 7nm lateral FinFET transistor reference. Finally, we draw conclusions of overall PPA benefits of this technology.
Hazar Yueksel, Ramon Bertran, et al.
MLSys 2020
Laura Bégon-Lours, Mattia Halter, et al.
MRS Spring Meeting 2023
Ying Zhou, Gi-Joon Nam, et al.
DAC 2023
Katja-Sophia Csizi, Emanuel Lörtscher
Frontiers in Neuroscience