J. Zhang, S. Pancharatnam, et al.
IEDM 2019
A novel integration process for self-aligned topvia Ru interconnects has been demonstrated, where lines are patterned through a subtractive scheme and vias are formed through a damascene scheme. TiN spacer has been utilized for improved etch selectivity to ensure self-aligned via patterning. Topvia structure should have a great advantage in increasing the percentage of lines with airgap and simulation results support that a significant reduction in capacitance can be achieved by incorporating airgaps in Ru topvia interconnects.
J. Zhang, S. Pancharatnam, et al.
IEDM 2019
H. Wu, V. Katragadda, et al.
IEDM 2021
K. Motoyama, Oscar Van der Straten, et al.
IITC 2012
P. Bhosale, N. Lanzillo, et al.
VLSI Technology 2021