Allen Gabor

Title

Distinguished Engineer

Bio

Allen Gabor is a Senior Technical Staff Member at IBM. He has worked in the field of lithography at Arch Chemicals, GlobalFoundries and IBM. This work has included photoresist development, CD control, overlay minimization and 193 dry, immersion and EUV insertion. He received his PhD (1996) in Materials Science and Engineering from Cornell University based on his work on block copolymer photoresists. He is the author of more than 50 journal papers and holder of over 30 patents. He currently serves on the program committee for SPIE Extreme Ultraviolet (EUV) Lithography Conference and is a senior member of SPIE.

Publications

Mix-and-match considerations for EUV insertion in N7 HVM
- - Xuemei Chen
  - Allen Gabor
  - et al.
- 2017
- SPIE Advanced Lithography 2017
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Advanced overlay control in volume manufacturing
- - Timothy Wiltshire
  - Christopher Ausschnitt
  - et al.
- 2011
- ASMC 2011
Overlay improvement roadmap: Strategies for scanner control and product disposition for 5-nm overlay
- - Nelson M. Felix
  - Allen H. Gabor
  - et al.
- 2011
- SPIE Advanced Lithography 2011
Smaller, smarter, faster, and more accurate: The new overlay metrology
- - Nelson M. Felix
  - Allen H. Gabor
  - et al.
- 2010
- SPIE Advanced Lithography 2010
Measuring layer-specific depth-of-focus requirements
- - Bernhard Liegl
  - Allen Gabor
  - et al.
- 2008
- SPIE Advanced Lithography 2008
Improving the power-performance of multicore processors through optimization of lithography and thermal processing
- - A. Gabor
  - T.A. Brunner
  - et al.
- 2007
- SPIE Advanced Lithography 2007
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- - Haoren Zhuang
  - Helen Wang
  - et al.
- 2007
- ISTC 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- - I. Ahsan
  - N. Zamdmer
  - et al.
- 2006
- VLSI Technology 2006

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Patents

- 31 Jan 2022
- US
- 11239077
Litho-etch-litho-etch With Self-aligned Blocks
- 25 Mar 2019
- US
- 10242952
Registration Mark Formation During Sidewall Image Transfer Process
- 06 Aug 2018
- US
- 10043760
Registration Mark Formation During Sidewall Image Transfer Process
- 01 Jan 2018
- US
- 9859224
Registration Mark Formation During Sidewall Image Transfer Process
- 17 Oct 2016
- US
- 9472506
Registration Mark Formation During Sidewall Image Transfer Process
- 02 Jun 2015
- US
- 9046788
Method For Monitoring Focus On An Integrated Wafer
- 30 Sep 2014
- US
- 8847416
Multi-layer Chip Overlay Target And Measurement
- 18 Mar 2014
- US
- 8673165
Sidewall Image Transfer Process With Multiple Critical Dimensions
- 17 Dec 2013
- US
- 8609322
Process Of Making A Lithographic Structure Using Antireflective Materials
- 26 Nov 2013
- US
- 8592110
Alignment Marks For Multi-exposure Lithography

Top collaborators

Allen Gabor

Title

Bio

Publications

Mix-and-match considerations for EUV insertion in N7 HVM

High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization

Advanced overlay control in volume manufacturing

Overlay improvement roadmap: Strategies for scanner control and product disposition for 5-nm overlay

Smaller, smarter, faster, and more accurate: The new overlay metrology

Measuring layer-specific depth-of-focus requirements

Improving the power-performance of multicore processors through optimization of lithography and thermal processing

Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond

High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography

RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology

Patents

Litho-etch-litho-etch With Self-aligned Blocks

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Method For Monitoring Focus On An Integrated Wafer

Multi-layer Chip Overlay Target And Measurement

Sidewall Image Transfer Process With Multiple Critical Dimensions

Process Of Making A Lithographic Structure Using Antireflective Materials

Alignment Marks For Multi-exposure Lithography

Top collaborators

Nelson Felix

Luciana Meli

Mary Breton