Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond

Abstract

Reducing the final tip-to-tip (T2T) distance of gate conductor line ends in SRAM cells to the desired target values has become one of the major patterning challenges for CMOS technologies with ground rules of 45 nm and beyond. T2T distance reduction can be achieved by optimization of lithography and reactive ion etch (RIE) processes of a single patterning approach or by a more complex double exposure/double etch (DE2) technique. The capability and limitations of these options for T2T distance reduction, applied individually or partly in combination, their overall process controllability and impact on other important process characteristics will be discussed for the first time to provide guidance for selecting the most suitable approach depending on the requirements of a particular SRAM cell design[1]. Improvements in SRAM standby leakage and NFET Idoff due to reduced T2T distance have been demonstrated.