Higher density semiconductor packaging is demanded for greater computation required for AI applications. 2.5D packaging solutions using an inactive Si substrate have been commercialized. However, due to its limited scalability and the high cost, 2.1D packaging technology using organic substrates is also pursued in the semiconductor industry. To archive a higher density circuity in the organic substrate, layer stacking processes consisting of both thin films and thin conductors on a conventional organic substrate have been reported. However, since these technologies result in an asymmetric substrate, a new substrate design method needs to be established in order to control the substrate thermal deformation induced by CTE mismatch of the constituent materials. In this work, a genetic algorithm is introduced to demonstrate the minimization of the thermal warpage of a substrate by optimizing the copper content in the conductor layers. A conventional asymmetric FR4 printed circuit board is investigated for demonstration. As the result, it is confirmed that the genetic algorithm can provide the optimal copper content value on each conductor layer with a practical computation time. This paper introduces and discusses the details of the algorithm, the technique that is logical to physical mapping required to execute and the results obtained.