Publication
IEEE Transactions on CPMT
Paper

3-D Die Stacking with 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System

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Abstract

In this letter, we have demonstrated a packaging technique for 3-D IC with Cu back-end-of-the line (BEOL) on a mixed pitch (55 and 75~\mu \text{m} ) advanced ground-rule laminate by developing a 3-D die-stack on substrate (3D-DSS) technology. 3-D DSS is a new assembly technology to address issues caused by warpage and mechanical stress response of 3-D integration packaging when bonding a thin through-silicon via (TSV) die on an organic substrate. The 35\,\,\text {mm} \times 35 mm test substrate has high density interconnects which include four wiring layers with thin film insulators on the chip mounting side of conventional buildup layers. A minimum 2 \mu \text{m} /2 \mu \text{m} line/space is constructed on this advanced ground-rule laminate. The experimental results showed that the 3-D DSS method can effectively prevent microbump opens or shorts, and can produce good solder joints between thin TSV die in a 3-D configuration on a fine, mixed pitch laminate.

Date

01 May 2021

Publication

IEEE Transactions on CPMT

Authors

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