3D die stacking of logic and memory die can greatly enhance system performance, by enabling the logic die to have high bandwidth, low latency, low energy access to memory. To demonstrate the concept of testing an AI (Artificial Intelligence) core through a 3D die, the following method was used. An AI core which was previously designed and tested was resynthesized along with a Pseudo Random Binary Sequencer (PRBS) along one edge of the die. In the same reticle set, a second die of the same dimensions was designed with an I/O (Input/Output) buffer and a similar PRBS along one edge. The second die was designed with Keep Out Zones (KOZ) so that TSVs (Through Silicon Vias) could be integrated in this die during the fabrication process. Wafers were then built to harvest the first and second dies. The wafers that were used to create the second dies were thinned to reveal TSVs, and subsequently diced into thinned individual die. The first and second dies were then attached in a vertical 3D die stack, which was further assembled onto an organic packaging substrate. The substrate was terminated with a BGA (Ball Grid Array).Both parametric and functional electrical tests were performed to understand effects of the 3D stacking. These tests were conducted by probing the BGA, to determine the response of the first die when it was tested through the 3D thinned die. Parametric testing verified that the introduction of the 3D die not cause shorts, opens, or additional variability in electrical parameters, while functional tests verified that the designed logic, with communication across the 3D interface, produced the expected outcome.The results indicate successful design and resynthesis of both the AI core and the I/O buffer, and successful TSV integration, grind side processing, and final 3D die stacking and assembly. The functional testing of the AI core showed excellent results when tested through the intermediate 3D die. This demonstrates viability of 3D stacking of AI cores and other functional die with an I/O buffer die.