Researchers at IBM and ASMPT have hit a milestone with a hybrid bonding technology that drastically reduces the I/O interconnection size of bonding needed between two chiplets, paving the way for a myriad of new computer chip designs.
Over the decades, computers have shrunk from machines that took up entire rooms to devices that fit on your wrist. Researchers have focused on increasing the density of the number of transistors on a single computer chip, and have generally relied on SOCs (or systems on a chip) to lower costs and make devices more compact. But we’re starting to approach the physical limits of how small we can make some parts of a chip, and other parts can be just as effective in certain use cases even when they’re not the smallest, most cutting-edge designs.
This is where the importance of chip packaging comes in. Packaging, the process of connecting integrated circuits on a chip or circuit board, has become more complex as electronic devices have shrunk and the components of chips themselves get smaller and smaller. IBM announced a chip with components just 2 nanometers in size in 2021. As the semiconductor industry moves towards new methods of chip construction, advances in packaging will grow in importance. And a key part of this shift is a rise in chiplet technology.
Research into chiplets has shown what the future of computing might look like. Instead of focusing on building monolithic SOCs, there are many emerging use cases (like training and running complex AI foundation models) that could benefit from new chip designs. The concept behind chiplets effectively breaks up a SOC into its composite parts (like GPUs, CPUs, I/O, and memory), and building up systems of chiplets that are more effective for a specific task. In the case of AI, you could build a chiplet system that combines a processing unit, an AI accelerator, and stacks of memory all communicating and sharing data almost as if they were all on the same chip.
One of the biggest hurdles that needs to be overcome in moving chiplets from research to production is the way that chiplets are bonded together during the packaging process. To date, most designs have used solder, or a combination of solder and copper, sitting on top of a metal pad, to bond chiplets together. These methods resulted in bonds that were between 150 and 30 microns and required very tight soldering to be effective. But a team of researchers at IBM and ASMPT, a major supplier of hardware and software for producing semiconductors, have been working on a new way to bond chiplets that drastically cuts down the amount of space.
In a paper presented this week at the 2023 IEEE Electronic Components and Technology Conference (ECTC),1 the researchers outlined their hybrid bonding concept. Their method fuses copper and an oxide in layers that are just a few atoms thick, using no solder. The result is a bond between chiplets that’s only around 0.8 microns, considerably slimmer than other methods currently being tested.
The new hybrid bonding method has the potential to increase the data throughput between chiplets, and the number of chiplets that could be installed in a given space, leading to a chiplet system that would act more like a single SOC. It has massive implications for integrating chiplet technology into smaller devices, for example, and increasing the performance of chiplets, or their energy efficiency.
In the team’s method, the toughest challenge was to ensure that the bonding was secure, removing potential moisture or air bubbles on a minuscule scale. Just three molecules of water between the bonding layers would be enough to break the connection between layers. Removing this hazard, along with air bubbles, while maintaining clean surfaces for the layers that are bonding together — and ensuring that this process could be reliably carried out again and again — were the main challenges the team sought to overcome in their research.
The team’s method is similar to how chip wafers are bonded, which is a standard industry practice at this point — just at a considerably smaller scale — and they’ve been using an ASMPT machine designed for die-to-wafer bonding to carry out their tests. While the team believes that their method would allow chiplets to be built and bonded together at scale, more work needs to be done on researching the tooling of ASMPT’s systems.
The systems of tomorrow are going to require new ways to solve computing problems as they become more complex and varied, and chiplets provide a potential pathway to solving those problems. With hybrid bonding, creating systems that act as if they were part of a single chip, that future comes sharper into view.
Date31 May 2023
Katsuyuki Sakuma, Roy Yu, Nicholas Polomoff, Luke Darling, Promod Chowdhury, Sathya Raghavan, Keodara Seifert, John Knickerbocker, Dale McHerron, Ming Li, Siu Cheung So, So Ying Kwok, Chun Ho Fan, Siu Wing Lau, “Voids-free Die-level Cu/ILD Hybrid bonding,” 2023 IEEE 73rd , Electronic Components and Technology Conference (ECTC), Florida, USA, 2023. ↩