Innovative BEOL Oxide-Based Devices as Key Enablers for High-Performing Heterogeneous Systems

Heterogeneous Integration to Sustain Compute Hardware Scaling: For decades, Moore’s Law has driven semiconductor progress through relentless transistor scaling (Fig.1). However, as silicon devices reach atomic dimensions, physical and economic barriers—such as power density, interconnect limitations, and escalating fabrication costs—slow traditional scaling [1]. At the same time, as shown in Fig. 2, AI’s rapid growth has exposed inefficiencies in conventional hardware, where memory access and data movement dominate power consumption, highlighting the need for new computing paradigms that minimize these bottlenecks [2]. To sustain innovation, the industry has shifted toward system-level scaling, where architectural advancements and heterogeneous integration (HI) play a central role [1,2] (Fig.1). Overview of Heterogeneous Integration: As shown in Fig. 3, rather than a one-size-fits-all approach, HI tailors computing hardware to specific applications, co-integrating logic, memory, sensing, and power management to optimize performance, efficiency, and functionality [2]. This is enabled by a combination of innovations across multiple layers in the system. Advancements in packaging technology play a critical role, encompassing new materials such as silicon, glass and polymers for improved thermal and electrical performance, as well as novel materials and geometries that enhance signal integrity and bandwidth. Electro-optic chip-level hybrid packages enable higher data throughput by tighter integration of the electronic and photonic domains [3]. Additionally, refined thermo-electrical management strategies at the package level are essential to maintain efficiency as power densities rise. Further scaling of chip-to-package interconnects to micrometer and sub-micrometer pitches enhances connectivity, reduces latency and power dissipation [4]. Alongside packaging innovations, new materials for interconnects, dielectrics, and semiconductors are driving performance improvements, while device-level advancements continue to push density and efficiency beyond conventional scaling [2]. HI adoption varies based on application needs: data-intensive AI accelerators require integrated processor-memory architectures to minimize data movement distances, favoring compute-in/near-memory systems. Edge computing prioritizes low-power, high-efficiency solutions for real-time processing with minimal energy consumption. While HI is a key enabler for system-level scaling, continued innovation within the die remains essential to address fundamental computing bottlenecks, particularly through advancements in BEOL monolithic integration. BEOL Device Innovation and its Contribution to Heterogeneous Integration: Functionalization of the Back-End-of-Line (BEOL) is emerging as a crucial approach, as this monolithic integration enhances area efficiency, reduces interconnect delays, and minimizes data transfer overhead [5-8]. In this context, oxide-based devices—including Resistive RAM (ReRAM), ferroelectric FETs, and oxide-channel transistors—are particularly promising for their ability to be fabricated in the BEOL of CMOS. This BEOL functionalization not only supports compute-in-memory architectures for AI acceleration but also enhances edge computing by enabling compact, low-power real-time processing [9-10]. In high-density storage, monolithic 3D memory structures built with these devices provide a path to scale beyond conventional memory devices [11]. Additionally, oxide transistors in BEOL can enable novel gain-cell designs for power-efficient memory and processing solutions [12]. An overview of BEOL oxide-based devices potential is shown in Fig. 3. Prospects and Challenges: HI is the main driver of computational performance advancement beyond Moore’s Law. However, some aspects of HI present significant challenges including material and process compatibility, complex interconnect and packaging requirements, thermal management issues, reliability concerns and high manufacturing costs. Progress requires stronger academia-industry collaboration to drive innovations in materials, fabrication, and system co-design. Over the next decade, advancements in monolithic 3D, functionalization of BEOL, chiplet architectures, and hybrid memory-compute paradigms will enable more compact, efficient, and high-performance systems beyond traditional scaling.

Acknowledgements: The authors acknowledge the BRNC at IBM Research Europe-Zurich. This work is funded by the European Union and Swiss state secretariat SERI within the H2020 MeM-Scales (grantID: 871371), MANIC (grantID: 861153), PHASTRAC (grantID: 101092096), CHIST-ERA UNICO (20CH21-186952), CONCEPT (grantID: 101135946), FIXIT (grantID: 101135398) and SNSF ALMOND (grantID: 198612) projects. References: [1] From ASML investor day 2021; [2] IEEE EPS, Heterogeneous Integration Roadmap 2024 Edition; [3] J. Knickerbocker et al., arXiv:2412.06570 (2024); [4] J.-C. Souriau, Chip-Scale Review, 37, (2024); [5] T. Stecconi et al., Nano Letters, 24, 866, (2024); [6] D. Falcone et al., arXiv:2502.04524, (2025); [7] M. Halter et al., Comm. Mater., 4, 14, (2023); [8] N. Gong et al., IEEE-IEDM, 33.7.1-4, (2022); [9] V. Clerico, IEEE-ISCAS., arXiv:2502.18152, (2025); [10] F. F. Athena et al., Front. In Electr., 4, 9, (2024); [11] Z. Wang et al., Int. J. Extrem. Manuf. 6 032006, (2024); [12] S. Liu et al., IEEE-IEDM 4, (2024).