A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
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120 results at IEEE JSSC
A 52 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- IEEE JSSC
A high-power and scalable 2-D phased array for terahertz CMOS integrated systems
- Yahya Tousi
- Ehsan Afshari
- 2015
- IEEE JSSC
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2014
- IEEE JSSC
A 0.6 v input CCM/DCM operating digital buck converter in 40 nm CMOS
- Xin Zhang
- Po-Hung Chen
- et al.
- 2014
- IEEE JSSC
A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2014
- IEEE JSSC
A flexible, event-driven digital filter with frequency response independent of input sample rate
- Christos Vezyrtzis
- Weiwei Jiang
- et al.
- 2014
- IEEE JSSC
A 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
1 Mb 0.41 μm2; 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert K. Montoye
- et al.
- 2014
- IEEE JSSC