Publication
IEEE JSSC
Paper

A high-power and scalable 2-D phased array for terahertz CMOS integrated systems

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Abstract

This work introduces a 2-D phased array architecture that is suitable for high power radiation at mm-Wave and Terahertz frequencies. We address the challenge of signal generation above the cut-off frequency of transistors by presenting a radiation method based on the collective performance of a large number of synchronized sources. As theory shows, both frequency locking/tuning and beam steering can be independently achieved by manipulating the local coupling between the nearest neighbors. This control method results in a dynamical network that is insensitive to array dimensions and is scalable to the point that can achieve a level of output power and spectral purity beyond the reach of conventional sources. To demonstrate the concept, we implement a 4×4 version of this phased array at 340 GHz using a 65 nm bulk CMOS process. The paper presents the design and implementation of the oscillators, couplings and the integrated antennas. The measured results at 338 GHz reveal a peak equivalent isotropically radiated power (EIRP) of +17.1 dBm and a phase noise of -93 dBc/Hz at the 1 MHz offset frequency. This chip presents the first fully integrated terahertz phased array on silicon. Furthermore, the output power is higher than any lens-less silicon-based source above 200 GHz and the phase noise is lower than all silicon radiating sources above 100 GHz.

Date

01 Feb 2015

Publication

IEEE JSSC

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