Solomon Assefa, Huapu Pan, et al.
OFC 2013
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is -110 dBc/Hz at 10 MHz offset. The 14 × 160 μm 2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply. © 1966-2012 IEEE.
Solomon Assefa, Huapu Pan, et al.
OFC 2013
Bodhisatwa Sadhu, Arun Paidimarri, et al.
IMS 2018
Ekaterina Laskin, Alexander Rylyakov
SiRF 2009
Montek Singh, Jose A. Tierno, et al.
ASYNC 2002