A gradient descent bias optimizer for oscillator phase noise reduction demonstrated in 45nm and 32nm SOI CMOS
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2018
- RFIC 2018
Publications
Date
Featured collections
Popular topics
27 results for Mark Ferriss
A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2016
- RFIC 2016
A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- RFIC 2015
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
A 46.4-58.1 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2014
- RFIC 2014
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
A 28GHz hybrid PLL in 32nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2013
- VLSI Circuits 2013
A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS
- Alberto Valdes-Garcia
- Arun Natarajan
- et al.
- 2013
- RFIC 2013
A 73.9-83.5GHz synthesizer with -111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology
- Jean-Olivier Plouchart
- Mark Ferriss
- et al.
- 2013
- RFIC 2013
A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution
- Li Li
- Michael P. Flynn
- et al.
- 2012
- A-SSCC 2012