Publication
VLSI Circuits 2013
Conference paper

A 28GHz hybrid PLL in 32nm SOI CMOS

Abstract

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140×160μm2 32nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply. © 2013 JSAP.

Date

17 Sep 2013

Publication

VLSI Circuits 2013

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