Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Publications
8 results for Kang-ill Seo
Predictive Simulations and Experimental Study of AlN Bonding for Better Thermal Dissipation in BSPDN
- Sarabjot Singh
- Sangshin Jang
- et al.
- 2025
- IITC 2025
Conference paperFirst Demonstration of 16nm Pitch Subtractive Ru Interconnects for Advanced Technology Nodes
- C. Penny
- K. Motoyama
- et al.
- 2025
- IITC 2025
Conference paperSubtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Conference paperVertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paperBottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
Conference paper10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
Conference paperInvestigation of fixed oxide charge and fin profile effects on bulk FinFET device characteristics
- Bomsoo Kim
- Dong-Il Bae
- et al.
- 2013
- IEEE Electron Device Letters
Paper