Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
- Ram Krishna
- Atom O. Watanabe
- et al.
- 2023
- ECTC 2023
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7 results for John Golz
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
Copper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits