ISSCC 2007
Conference paper

A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier

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A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces a performance-enhancing 3T micro sense amplifier architecture (μSA). The macro was characterized via a testchip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85°C and low voltage operation with a 600mV supply. © 2007 IEEE.