High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Publications
198 results for Vijay Narayanan
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t-tuning dipoles with gate-first process
- T. Ando
- M.M. Frank
- et al.
- 2009
- IEDM 2009
Interaction of La2O3 capping layers with HfO 2 gate dielectrics
- M. Copel
- S. Guha
- et al.
- 2009
- Applied Physics Letters
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
- K. Choi
- H. Jagannathan
- et al.
- 2009
- VLSI Technology 2009
pFET V t control with HfO 2/TiN/poly-Si gate stack using a lateral oxygenation process
- B. Cartier
- M. Steen
- et al.
- 2009
- VLSI Technology 2009
Interfacial layer optimization of high-k/metal gate stacks for low temperature processing
- Barry P. Linder
- Vijay Narayanan
- et al.
- 2009
- Microelectronic Engineering
Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)
- Martin M. Frank
- SangBum Kim
- et al.
- 2009
- Microelectronic Engineering
Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes
- Changhwan Choi
- Takashi Ando
- et al.
- 2009
- Microelectronic Engineering
Engineering band-edge high-κ/metal gate n-MOSFETs with cap layers containing group IIA and IIIB elements by atomic layer deposition
- H. Jagannathan
- L.F. Edge
- et al.
- 2009
- ECS Meeting 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008