VLSI Technology 2009
Conference paper

Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond


We report for the first time that extreme EOT scaling and low n/p V THs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low VTHs and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.