Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
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194 results for Vijay Narayanan
Characterization and optimization of charge trapping in high-k dielectrics
- Eduard Cartier
- Takashi Ando
- et al.
- 2013
- IRPS 2013
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013
Aggressive sige channel gate stack scaling by remote oxygen scavenging: Gate-first pFET performance and reliability
- Martin M. Frank
- Eduard A. Cartier
- et al.
- 2012
- ECS Meeting 2012
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011