In this paper we report on a comprehensive study of Silicon-Germanium channel (cSiGe) physics, layout effects and impact on device performance. This work demonstrates a 2nd generation of dual channel technology, which meets the 22nm high performance technology (HP) requirement. Modeling and simulation are used to optimize the process to obtain a 10% Short Channel Effect (SCE) improvement and an overall 20% performance enhancement. This 2 nd generation high performance dual channel process has been integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology. © 2013 IEEE.