Wafer-level integration of embedded cooling approaches

Abstract

New thermal management solutions to keep components within thermal limits are needed to fully exploit the potential of 3D integration of ICs yielding dense electronic systems with increased performance and power efficiency. A roadmap from embedded single-side towards 3D interlayer cooling is presented. The characteristics of single-phase water and two-phase dielectric cooling are discussed further. Dual-side cooling was identified as an intermediate step considering an active cooled interposer combining thermal and electrical functionality. Finally, various design aspects for interlayer cooling in 3D chip stacks are listed that can leverage wafer-level bonding as cost-efficient implementation of such cooling concepts.