In this study, a dual-side cooling topology based on a silicon cold plate and an electrical functional silicon-interposer with embedded fluid channels is benchmarked against mere back-side cooling. The back-side cold plate can be operated in a split-flow mode, whereas in the case of the interposer only a single in-and outlet can be implemented, which results in a cross-flow heat-exchange mode. An interposer cavity can be achieved by back-to-back bonding of interposer shells to achieve large channel heights. Sealing-ring structures and embedded TSVs are required to prevent contact between water and the electrically active TSVs. Optimal micro-channel dimensions of 150 μm width and 250 μm height were computed using an analytical convection model that considered mass and heat transfer. The impact of thermal interfaces arising from the electrical interconnects between the chip stack and the interposer was studied by numerical heat-conduction modeling. Neither, the interconnect type, rail or pillar, nor the application of thermally conductive underfills did result in significant changes in junction temperature. However, the dual-side cooling approach resulted in twice lower thermal gradients at the inlet of the cavity than with the back-side or front-side cooling option only. Although the cross-flow mode of the interposer increases the coolant temperature more than the cold plate, dual-side cooling extends the power dissipation limit for single dies and chip stacks substantially, supporting performance and efficiency scaling.