Microelectronic Engineering

Processing and moisture effects on TDDB for Cu/ULK BEOL structures

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As scaling in Cu/BEOL structures causes critical dimensions to shrink, TDDB between Cu lines is increasingly becoming a reliability concern and increasingly limiting the choices of low-k and ULK materials which can be implemented [1]. Failure analysis has shown that the interface between the dielectric and the Cu capping layer is typically where dielectric breakdown occurs. This interface can be adversely affected by a number of processing steps and processing parameters including dicing, CMP, queue time between Cu CMP and Cu capping, and exposure to moisture [2-5]. In this study we examine the effect of these critical processing steps and parameters on TDDB. To focus on the effect of the processing steps and to minimize the effects of wafer to wafer and lot to lot variability, we have primarily used structures with Cu line spacings of 80-90 nm. For some IV experiments a spacing of 30-40 nm was used. Techniques for improving TDDB performance are also discussed. © 2011 Elsevier B.V. All rights reserved.