Aditya Bansal, Rahul Rao, et al.
IRPS 2009
We propose an asymmetric-MOSFET-based sixtransistor (6T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology. © 2009 IEEE.
Aditya Bansal, Rahul Rao, et al.
IRPS 2009
Aditya Bansal, Jae-Joon Kim, et al.
IRPS 2012
Aditya Bansal, Jae-Joon Kim, et al.
VLSID 2008
Ik Joon Chang, Jae-Joon Kim, et al.
ISLPED 2006