Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors

Abstract

We propose an asymmetric-MOSFET-based sixtransistor (6T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology. © 2009 IEEE.