Overcoming research challenges for CMOS scaling: Industry directions

Abstract

The development of silicon technology has been, and will continue to be, driven by system needs. The continuous and systematic increase in transistor density and performance, guided by CMOS scaling theory [1] and described in "Moore's Law" [2], has been a highly successful process for the development of silicon technology for the past 40 years. As the silicon industry moves into the 45 nm node and beyond, significant technology challenges will be imposed by silicon CMOS device scaling. Two of the most important challenges are the growing standby power dissipation and the increasing variability in device characteristics. These complaints are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. They are frequently cited as the reason Moore's Law is "broken", or why CMOS scaling is coming to an end. Industry directions for addressing these challenges are developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure; expanding the level of integration through three-dimensional structures comprised of silicon through-via holes and chip stacking in order to enhance functionality and parallelism; and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials, and new processes, such as spintronics, carbon nanotubes, nanowires, or molecular systems. © 2006 IEEE.