Scalability options for future SRAM memories

Abstract

As CMOS technology approaches the limits of scaling, device dimensions become similar in magnitude to the discrete structures and components of the device itself. Random process variations quickly are becoming a major limitation to limiting manufacturing yields. The 6T-SRAM cell has become the first casualty to these scaling effects, and has increased in size relative to larger logic components in recent technology nodes. Physical and electrical modifications to the SRAM cell and peripheral circuits can provide additional tolerance and allow continued scaling into the foreseeable future. This paper examines this issue and suggests some alternative structures that have been demonstrated to provide improvements. © 2006 IEEE.