35 GHz/35 psec ECL pnp technology
J. Warnock, P.F. Lu, et al.
IEDM 1990
This letter describes a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance ECL applications. The technology features 0.8-µm design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel accoupled active-pull-down (APD) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz have been demonstrated using this technology. © 1989 IEEE
J. Warnock, P.F. Lu, et al.
IEDM 1990
Tze-Chiang Chen, Suryadever Basvaiah, et al.
IEEE T-ED
John D. Cressler, Tze-Chiang Chen, et al.
IEEE T-ED
Kai-Yap Toh, C.T. Chuang, et al.
Bipolar Circuits and Technology Meeting 1990