Lower resistance scaled metal contacts to silicide for advanced CMOS

Abstract

A key challenge for high performance CMOS devices is the external parasitic resistance. This paper addresses scaling trends of contact level and discusses emerging constraints related to the properties of materials used in the current technology. Experimental and theoretical data presented herein are critical in understanding CA challenges beyond the 45 nm technology node and show great potential for copper as the alternative to tungsten process for CA metallization. © 2006 IEEE.