VLSI Technology 2013
Conference paper

High-performance Si1-xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions


We demonstrate for the first time, Si1-xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance SiGe-channel PFETs with oncurrent ION = 1.1 mA/μm at off-current IOFF = 100 nA/μm and supply voltage VDD = 1 V, which is attributed to high hole source injection velocity vx0 exceeding 1 × 107 cm/s. © 2013 JSAP.