IEEE Journal of Solid-State Circuits

Flexible test mode approach for 256-Mb DRAM

View publication


This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 10000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t RAS wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed.