As the semiconductor industry continues pushing Moore's law to the next node, interconnect structures scaling will be a key element to performance improvement of functional devices. However, the requirements for low LCDU and defectivity of these interconnect structures have become more stringent with continuous scaling. In this paper, a fundamental study is conducted to understand the impact of various factors on the patterning of EUV single exposure vias, and to find effective strategies to shrink CD while improving LCDU and defectivity. The work is based on a 40 nm pitch orthogonal via array baseline, and probes different patterning factors including illumination, resist materials, stack, scanner, and develop methods for LCDU improvement and defectivity reduction. The patterns are transferred to bottom dielectrics to study the evolution of LCDU and defectivity during etching.