The paper demonstrates the scalability of the dual damascene (DD) integration scheme below 28 nm pitch. We evaluate the performance of the 10 nm wide interconnects build using two process flows (i) Cu reflow with selectively deposited TaN barrier (Cu/R-TaN/SB), (ii) Cobalt/Copper composite (Co/Cu comp). These process innovations enable a significant improvement in via, signal and power line resistances. We discuss the corresponding implications towards performance in terms of signal delay, parasitic voltage, and FPG gain analysis. Our simulations show that the DD Cu interconnects formed using Cu/R-TaN/SB can enable next-generation (20-24nm pitch) low power mobile-like design solutions. The Co/Cu comp with high aspect ratio power rails provides the best performance for high-performance computing (HPC) applications.