Design and Experimental Technology for 0.1-μm Gate-Length Low-Temperature Operation FET's

Abstract

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1- μ m gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 μm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.