We study soft error rates (SER) in VLSI circuits, where the charge capable of causing a soft error becomes only a few percent of that created by a typical α-particle impacting on the circuits. Theoretical investigations are done considering a DRAM test vehicle, with the assumption that it is exposed to α-particlcs emanating from materials on the chip. We examine the effects of scaling on the SER and investigate the performance of several device structural modifications that can be introduced to decrease SER. We present experimental results on the achieved reduction in the charge that surface nodes collect when structural modifications are introduced. We find, both experimentally and theoretically, that the most promising modification is the incorporation of a buried grid of opposite conductivity type from the substrate. In general, however, as stored charge shrinks, multiple errors become prevalent, and SER reduction due to fabrication changes becomes less effective. Copyright © 1982 by the Institute of Electrical and Electronics Engineers, Inc.