Publication
VLSI Circuits 2017
Conference paper

A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET

View publication

Abstract

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10-12) at 60Gb/s with a frequency tracking range of ±600ppm. The measured sinusoidal JTOL indicates a corner frequency of 80MHz, with high frequency JTOL of 0.16UIpp at-5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.

Date

10 Aug 2017

Publication

VLSI Circuits 2017

Authors

Share