Conference paper

A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI

View publication


A transmitter for data (DQ) lines in a DDR3/4 memory link is presented. The transmitter supports a drive impedance range of 24-40 ω, operates from a 0.8-1.6 V supply range, and runs between 0.8 and 5.0 Gb/s. The DDR TX includes a clock-feathering-based slew rate control with duty cycle adjustment and uses thin oxide output stages for power saving. The power supply for the thin oxide pull-up protection is provided by an on-chip voltage regulator. Also FFE with 1 postcursor tap and max. 9.5 dB de-emphasis at 40 ω is included. Results measured with typical DDR settings such as 30 ω drive impedance and 1.35 V supply show a 1.2-5.8 V/ns slew rate range into a 50 ω termination, an energy efficiency at 2133 Mb/s of 4.4 pJ/bit and TJ (BER 10-12) of 26 ps. The transmitter is fabricated in 22-nm CMOS SOI and has a size of 132 × 83 μm2.