An efficient and accurate schematic transistor model of FinFET parasitic elements

Abstract

We present a schematic transistor model for multi-finger multi-fin FETs, which greatly simplifies an initially complex network. The schematic FinFET model accepts information about various aspects of the layout and is accurate in predicting overall FinFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a FinFET.