0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
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32 results for Jeffrey B. Johnson
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
- Siyu Koswatta
- N. Mavilla
- et al.
- 2015
- IEDM 2015
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- B. Yang
- R. Takalkar
- et al.
- 2008
- IEDM 2008
SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps
- M. Khater
- J.-S. Rieh
- et al.
- 2004
- IEDM 2004
Low thermal budget antimony/phosphorus NMOS technology for CMOS
- D.L. Harame
- E. Ganin
- et al.
- 1991
- IEDM 1991
Efficient and accurate schematic transistor model of FinFET parasitic elements
- Ning Lu
- Terence B. Hook
- et al.
- 2013
- IEEE Electron Device Letters
Modeling and analysis of transistor mismatch due to variability in short-channel effect induced by random dopant fluctuation
- Nauman Z. Butt
- Jeffrey B. Johnson
- 2012
- IEEE Electron Device Letters
Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond
- Jeffrey B. Johnson
- Terence B. Hook
- et al.
- 2008
- IEEE Electron Device Letters