VLSI Circuits 2011
Conference paper

An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects


A serial I/O chip set in 45nm SOI CMOS is mounted via 50μm pitch micro-C4 bumps to a silicon carrier and communicates over ultra-dense interconnects with pitches of between 8μm and 22μm. With DFE-IIR RX equalization, data is received over distances up to 6cm with channel losses as high as 16.3dB. The energy efficiency is better than 6.1pJ/bit. © 2011 JSAP (Japan Society of Applied Physi.