A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- Sergey V. Rylov
- Troy Beukema
- et al.
- 2016
- ISSCC 2016
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46 results for Benjamin D. Parker
A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- ISSCC 2015
A compact 4-chip package with 64 embedded dual-polarization antennas for W-band phased-array transceivers
- Xiaoxiong Gu
- Duixian Liu
- et al.
- 2014
- ECTC 2014
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
- M. Meghelli
- S. Rylov
- et al.
- 2006
- ISSCC 2006
A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
- M. Sorna
- T. Beukema
- et al.
- 2005
- ISSCC 2005
A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
- M. Sorna
- T. Beukema
- et al.
- 2005
- ISSCC 2005
SiGe BICMOS 3.3V clock and data recovery circuits for 10Gb/s serial transmission systems
- M. Meghelli
- B. Parker
- et al.
- 2000
- ISSCC 2000
Single-chip 4×500Mbaud CMOS transceiver
- A.X. Widmer
- K. Wrenner
- et al.
- 1996
- ISSCC 1996
Single-chip 1062 Mbaud CMOS transceiver for serial data communication
- J.F. Ewen
- A.X. Widmer
- et al.
- 1995
- ISSCC 1995