Conference paper

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os

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In this paper, we present a digital equalizer for 16Gb/s backplane I/Os which consumes only 3.5pJ/bit for an 8-tap FFE and 4+4 tap DFE operation. Several design choices were chosen to enable low power consumption at high speed. First, the FFE leverages parallelism to lower the supply voltage, while the DFE runs from a higher supply to close the feedback loop. Second, the FFE uses distributed arithmetic to reduce the number of required additions. Third, the DFE taps leave a window of four equalizer taps, which are covered by the FFE, in order to close the timing. Finally, a custom digital design style was chosen, which enabled the optimization of critical blocks and wires. At 0.6V supply, the FFE was measured to consume 1pJ/bit, while the DFE consumes 1.6pJ/bit at 0.9V while running at 16Gb/s.