About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
VLSI Circuits 2017
Conference paper
A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
Abstract
This paper presents a 28.05Gb/s transceiver in 32nm SOI CMOS technology. The receiver employs a quarterrate triple-speculation architecture. Techniques are introduced to adapt for mismatches in tap weights, gains and sampling phases. Error-free signaling at 28.05Gb/s is demonstrated with the transceiver over a 48dB loss backplane channel. In a four-port configuration, the power consumption at 28.05Gb/s is 484mW/lane, giving a FOM of 0.36mW/Gb/s/dB.