Publications

8 results for Daniel Storaska

A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- - Gautam Gangasani
  - John F. Bulzacchelli
  - et al.
- 2017
- VLSI Circuits 2017
A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- - Gautam R. Gangasani
  - Chun-Ming Hsu
  - et al.
- 2014
- IEEE JSSC
A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology
- - Gautam R. Gangasani
  - John F. Bulzacchelli
  - et al.
- 2013
- A-SSCC 2013
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- - John F. Bulzacchelli
  - Christian Menolfi
  - et al.
- 2012
- IEEE JSSC
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
- - John Bulzacchelli
  - Troy Beukema
  - et al.
- 2012
- ISSCC 2012
10+ Gb/s 90-nm CMOS serial link demo in CBGA package
- - Sergey Rylov
  - Scott Reynolds
  - et al.
- 2005
- IEEE Journal of Solid-State Circuits
10+ Gb/s 90nm CMOS serial link demo in CBGA package
- - Sergey Rylov
  - Scott Reynolds
  - et al.
- 2004
- CICC 2004
A 7F² cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- - Heinz Hoenigschmid
  - Alexander Frey
  - et al.
- 2000
- IEEE Journal of Solid-State Circuits