Benjamin G. Lee, Joris Van Campenhout, et al.
CLEO 2010
This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM.
Benjamin G. Lee, Joris Van Campenhout, et al.
CLEO 2010
Clint L. Schow, Alexander V. Rylyakov, et al.
IEEE Photonics Technology Letters
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
Daniel M. Kuchta, Alexander V. Rylyakov, et al.
OFC 2014