A 20-ns 128-Kbit X 4 High-Speed DRAM with 330-Mbit/s Data Rate

Abstract

This paper describes a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kbit X 4, 78-mm2 chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25°C, and 50-pF load. A 256-bit X 4 high-speed page mode is provided which has 12-ns cycle into 60 pF, which results in a data rate of 330 Mbit/s. Additional measurements on the HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. © 1988 IEEE