SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
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30 results for Robert Franch
A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic
- S. Subbanna
- D.L. Harame
- et al.
- 1993
- IEDM 1993
A 1.2 ns/1 ns 1 K∗16 ECL dual-port cache RAM
- Hyun J. Shin
- P.F. Lu
- et al.
- 1993
- ISSCC 1993
A New Failure Mode of Radiation-Induced Soft Errors in Dynamic Memories
- T.V. Rajeevakumar
- Nicky C. C. Lu
- et al.
- 1988
- IEEE Electron Device Letters
POWER8 design methodology innovations for improving productivity and reducing power
- Matthew M. Ziegler
- Ruchir Puri
- et al.
- 2014
- CICC 2014
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
On-chip timing uncertainty measurements on IBM microprocessors
- R.L. Franch
- P. Restle
- et al.
- 2008
- IEEE ITC 2008
Impact of Self-Heating on Digital SOI and Strained-Silicon CMOS Circuits
- Keith A. Jenkins
- R.L. Franch
- 2003
- IEEE International SOI Conference 2003
Optical measurement of internal logic patterns in a flip-chip mounted silicon SRAM integrated circuit
- H. Heinrich
- N. Pakdaman
- et al.
- 1992
- LEOS 1992
Advances in Membrane Probe Technology
- J. Kister
- R.L. Franch
- 1992
- IEEE ITC 1992