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Publication
ASIC/SOC 2002
Conference paper
Long-term power minimization of dual-νΤ CMOS circuits
Abstract
In this paper, we define Long-Term power dissipation in which the effect of the system-level power management on the total power dissipation of a given circuit is considered. Then, we present a novel design methodology to minimize the Long-Term power dissipation of a circuit used along with dual-threshold voltage selection and voltage scaling. In simulation on 16-bit carry lookahead adders (CLAs), the proposed approach can reduce up to 80% and 25% of the total power dissipation along with clock- and power-gating, respectively.