Gouranga Charan, Abinash Mohanty, et al.
IEEE JXCDC
This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance.
Gouranga Charan, Abinash Mohanty, et al.
IEEE JXCDC
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, et al.
VLSI Circuits 2004
Gokul Krishnan, Li Yang, et al.
IEEE TC
Rajiv V. Joshi, Yuen Chan
ESSCIRC 2005